SIHD3N50D d series power mosfet features ?optimal design - low area specific on-resistance - low input capacitance (c iss ) - reduced capa citive switching losses - high body diode ruggedness - avalanche energy rated (uis) ? optimal efficiency and operation - low cost - simple gate drive circuitry - low figure-of- merit (fom): r on x q g - fast switching ? material categorization: for definitions of compliance please see applications ? consumer electronics - displays (lcd or plasma tv) ? server and telecom power supplies - smps ? industrial - welding - induction heating - motor drives ? battery chargers notes a. repetitive rating; puls e width limited by maximum junction temperature. b. v dd = 50 v, starting t j = 25 c, l = 2.3 mh, r g = 25 ? , i as = 2.8 a. c. 1.6 mm from case. d. i sd ? i d , starting t j = 25 c. product summary v ds (v) at t j max. 550 r ds(on) max. ( ? ) at 25 c v gs = 10 v 3.2 q g (max.) (nc) 20 q gs (nc) 3 q gd (nc) 5 configuration single n-channel mosfet g d s dpak (to-252) s d g ordering information package dpak (to-252) lead (pb)-free SIHD3N50D-e3 lead (pb)-free and halogen-free SIHD3N50D-ge3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 500 v gate-source voltage v gs 30 gate-source voltage ac (f > 1 hz) 30 continuous drain current (t j = 150 c) v gs at 10 v t c = 25 c i d 3.0 a t c = 100 c 1.9 pulsed drain current a i dm 5.5 linear dera ting factor 0.56 w/c single pulse avalanche energy b e as 9mj maximum power dissipation p d 104 w operating junction and storage temperature range t j , t stg - 55 to + 150 c drain-source voltage slope t j = 125 c dv/dt 24 v/ns reverse diode dv/dt (d) 0.22 soldering recommendations (peak temperature) c for 10 s 300 c www.freescale.net.cn www.freescale.net.cn 1 / 9
notes a. repetitive rating; puls e width limited by maximum junction temperature. b. c oss(er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 % to 80 % v dss . c. c oss(tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 % to 80 % v dss . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -62 c/w maximum junction-to-case (drain) r thjc -1.8 specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 500 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 250 a - 0.56 - v/c gate-source threshold voltage (n) v gs(th) v ds = v gs , i d = 250 a 3 - 5 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 500 v, v gs = 0 v - - 1 a v ds = 400 v, v gs = 0 v, t j = 125 c - - 10 drain-source on-state resistance r ds(on) v gs = 10 v i d = 2.5 a - 2.6 3.2 ? forward transconductance a g fs v ds = 8 v, i d = 1.5 a - 1 - s dynamic input capacitance c iss v gs = 0 v, v ds = 100 v, f = 1 mhz - 175 - pf output capacitance c oss -21- reverse transfer capacitance c rss -5- effective output capacitance, energy related b c o(er) v ds = 0 v to 400 v, v gs = 0 v -21- effective output capacitance, time related c c o(tr) -26- total gate charge q g v gs = 10 v i d = 1.5 a, v ds = 400 v -612 nc gate-source charge q gs -2- gate-drain charge q gd -3- turn-on delay time t d(on) v dd = 400 v, i d = 1.5 a r g = 9.1 ? , v gs = 10 v -1224 ns rise time t r -918 turn-off delay time t d(off) -1122 fall time t f -1326 gate input resistance r g f = 1 mhz, open drain - 3.3 - ? drain-source body diode characteristics continuous source-dra in diode current i s mosfet symbol showing the integral reverse p - n junction diode --3 a pulsed diode forward current i sm --12 diode forward voltage v sd t j = 25 c, i s = 1.5 a, v gs = 0 v - - 1.2 v reverse recovery time t rr t j = 25 c, i f = i s = 1.5 a, di/dt = 100 a/s, v r = 20 v - 293 - ns reverse recovery charge q rr -0.74-c reverse recovery current i rrm -5-a s d g SIHD3N50D d series power mosfet www.freescale.net.cn 2 / 9
typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 0 t j = 25 c top 15 v 14 v 13 v 12 v 11 v 10 v 9 v 6 v 7 v 8 v 0 5 10 15 20 25 30 1 2 3 4 5 6 v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 1 01020 0 4 2 3 t j = 150 c 5152530 top 15 v 14 v 13 v 12 v 11 v 10 v 9.0 v 8.0 v 7.0 v 6.0 v 5.0 v v gs , gate-to-source voltage (v) i d , drain-to-source current (a) 010 25 51520 0 t j = 150 c t j = 25 c 1 2 3 4 5 6 t j , junction temperature (c) r d s (on) , drain-to- s ource 2.5 0.5 - 60 3 2 1.5 1 0 - 40 - 20 0 20 40 60 80 100 120 140 160 v gs = 10 v i d = 1.5 a on re s i s tance (normalized) 1 10 100 1000 0 100 200 300 400 500 v d s , drain-to- s ource voltage (v) capacitance (pf) c i ss c o ss c r ss v gs = 0 v, f = 1 mhz c i ss = c g s + c gd , c d s s horted c r ss = c gd c o ss = c d s + c gd q g , total g ate charge (nc) v gs , g ate-to- s ource voltage (v) 16 4 0 24 20 12 8 3 6 9 12 v d s = 400 v v d s = 250 v v d s = 100 v 0 SIHD3N50D d series power mosfet www.freescale.net.cn 3 / 9
fig. 7 - typical source-dra in diode forward voltage fig. 8 - maximum safe operating area fig. 9 - maximum drain curre nt vs. case temperature fig. 10 - typical drain-to-source voltage vs. temperature fig. 11 - normalized thermal transient impedance, junction-to-case v s d , s ource-drain voltage (v) i s d , rever s e drain current (a) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 t j = 150 c t j = 25 c v gs = 0 v 0.01 0.1 1 10 100 v d s , drain-to- s ource voltage (v) i d , drain current (a) 0.01 0.1 1 10 100 1 10 100 1000 * v gs > minimum v gs at which r d s (on) i s s pecied operation in thi s area limited by r d s (on) bvd ss limited t c = 25 c t j = 150 c s ingle pul s e 100 s 1 m s 10 m s limited by r d s (on) * t j , case temperature (c) i d , drain current (a) 25 50 75 100 125 150 0 0.5 1.0 1.5 2.0 2.5 3.0 t j , junction temperature (c) v ds , drain-to-source - 60 0 160 brakdown voltage (v) - 40 - 20 20 40 60 80 100 120 140 475 500 525 550 575 600 625 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 normalized effective tran s ient thermal impedance pul s e time ( s ) duty cycle = 0.5 0.1 s ingle pul s e 0.2 0.02 0.05 SIHD3N50D d series power mosfet www.freescale.net.cn 4 / 9
fig. 12 - switching time test circuit fig. 13 - switching time waveforms fig. 14 - unclamped inductive test circuit fig. 15 - unclamped inductive waveforms fig. 16 - basic gate charge waveform fig. 17 - gate charge test circuit pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f r g i as 0.01 t p d.u.t l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + - SIHD3N50D d series power mosfet www.freescale.net.cn 5 / 9
fig. 18 - for n-channel p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd SIHD3N50D d series power mosfet www.freescale.net.cn 6 / 9
to-252aa (high voltage) notes 1. package body sizes exclude mold flash, protrusion or gate bu rrs. mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. package body sizes determined at the outermo st extremes of the plastic body exclusive of mold flas h, gate burrs and interlea d flash, but including any mismatch between the top and bottom of the plastic body. 3. the package top may be smaller than the package bottom. 4. dimension "b" does not include dambar prot rusion. allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimens ion at maximum material condition. the dambar cannot be located on the lower radius of the foot. e b 3 l3 l4 b 2 e b d h e1 d1 a c2 l1 l2 c a1 l millimeters inches dim. min. max. min. max. e 6.40 6.73 0.252 0.265 l 1.40 1.77 0.055 0.070 l1 2.743 ref 0.108 ref l2 0.508 bsc 0.020 bsc l3 0.89 1.27 0.035 0.050 l4 0.64 1.01 0.025 0.040 d 6.00 6.22 0.236 0.245 h 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 0.215 e 2.286 bsc 0.090 bsc a 2.20 2.38 0.087 0.094 a1 0.00 0.13 0.000 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 d1 5.30 - 0.209 - e1 4.40 - 0.173 - 0' 10' 0' 10' ecn: s-81965-rev. a, 15-sep-08 dwg: 5973 SIHD3N50D d series power mosfet www.freescale.net.cn 7 / 9
recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index SIHD3N50D d series power mosfet www.freescale.net.cn 8 / 9
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